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Intel plans to reveal some peculiarities of its dual-core processors, including dual-core Itanium-series processor designed for high-end servers, at IEEE International Solid-State Circuits Conference that begins today in San Francisco, California. The Intel Itanium 2 processor code-named Montecito that is to ship this year will not only bring platform-related enhancements, but will also deliver nearly tripled performance in certain application compared to today’s chips.


Intel Talks Dual-Core Itanium

Intel’s IA64 dual-core chip code-named Montecito is to be made using 90nm process technology and contain 1.72 billion transistors. The chip is expected to provide performance of up to 2.9 times higher compared to today’s top Itanium 2 processor, the 1.60GHz model with 9MB of cache. Still, the Montecito is projected to be a better power saver – at the same clock-speed it is claimed to consume 100W of power, 30W lower compared to contemporary flagship Itanium 2 product.

Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.

more @ http://www.xbitlabs.com/news/video/d...207105203.html

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