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18th February 2019, 07:45 | #1 |
[M] Reviewer Join Date: May 2010 Location: Romania
Posts: 148,618
| Western Digital’s RISC-V "SweRV" Core Design Released For Free Western Digital has published a register-transfer level (RTL) design abstraction of its in-house designed SweRV RISC-V core. The SweRV core is one of several RISC-V projects the company as undertaken as part of their effort to spearhead the ISA, its ecosystem, and foster their own transition away from licensed, royalty-charging CPU cores. In accordance with the more open design goals of RISC-V, the publication of the high-level representation of SweTV means that third parties can use it in their own chip designs, which will popularize not only the particular core design, but also the RISC-V architecture in general. https://www.anandtech.com/show/13964...eased-for-free |
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