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Via reveals C5J processor details Via reveals C5J processor details
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Via reveals C5J processor details
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Old 19th May 2004, 10:37   #1
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Default Via reveals C5J processor details

VIA HAS REVEALED details of its C5J Esther processor core, created using IBM's 90 nanometre SOI (silicon on isolator) process.
The core, claims Via, gives the processor an improved turn of speed and reduces power consumption to 3.5W at 1GHz. Via claims the core will allow unprecedented performance for demanding applications, like high compression video streaming and data encryption.

The C5J will also feature RSA encryption, Secure Hashing and support for execution protection to help fight e-mail worms and viruses. The NX feature, according to Via, "marks memory with an attribute that code should not be executed from that memory," assisting the battle against malicious code. NX protection will be supported with Windows XP SP2 Service Pack 2.

As well as that, the core includes a front side bus of up to 800MHz, a larger L2 cache, and SSE2/SSE3 multimedia instructions.

Via staged demonstrations of their PadLock Hardware Security Suite and other products of theirs at the Embedded Processor Forum 2004, where they also announced the C5J. It will show off this and other stuff at its Technical Forum in Old Taipei, during the Computex trade show.
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