Stefan Mileschin

One of the side announcements made during TSMC’s Technology Symposium was that it already has customers on hand with product development progressing for its future 3nm process node technology. As we’ve reported on previously, TSMC is developing its 3nm for risk production next year, and high volume manufacturing in the second half of 2022, so at this time TSMC’s lead partners are already developing their future silicon on the initial versions of the 3nm PDKs.

One company highlighted during TSMC’s presentations was Graphcore. Graphcore is an AI silicon company that makes the IPU, an ‘Intelligence Processing Unit’, to accelerate ‘machine intelligence’. It recently announced its second generation Colossus Mk2 IPU, built on TSMC’s N7 manufacturing process, and featuring 59.2 billion transistors. The Mk2 has an effective core count of 1472 cores, that can run ~9000 threads for 250 Teraflops of FP16 AI training workloads. The company puts four of these chips together in a single 1U to enable 1 Petaflop, along with 450 GB of memory and a custom low-latency fabric design between the IPUs.

A future generation of products from Graphcore, according to the TSMC presentation, is set to be developed with the TSMC 3nm process in mind, skipping TSMC’s 5nm. No exact timescale was presented, nor any indication of Graphcore’s strategy. As we can see from the slide, the Colossus IPU line involves big high-transistor count chips, using the extra transistor budget afforded by the more dense process node.

https://www.anandtech.com/show/16040...eration-on-3nm