Stefan Mileschin

Phison and Everspin on Wednesday said that the former's upcoming controllers for enterprise-grade SSDs would natively support the latter’s spin torque transfer MRAM (STT-MRAM) that will be used as a write buffer to enable a more effective I/O management. The new technology will allow makers of SSDs to improve I/O performance of their drives and enable power loss protection without usage of supercapacitors.

The upcoming eSSD controllers from Phison will support Everspin’s 1 Gb STT-MRAM memory “to increase the reliability and performance” of next-gen server-grade SSDs. In particular, the companies say that STT-MRAM chips will enable SSD makers to more effectively manage I/O streams, which will enable for better latency determinism and therefore improve QoS. Besides, since STT-MRAM is nonvolatile, drives that will use it instead of traditional DRAM buffers will not need a sophisticated power loss protection enabled by supercapacitors, which will simplify their physical architecture and will enable to increase their capacity by adding more 3D NAND packages.

As far as performance of STT-MRAM-enabled SSDs is concerned, the buffer and appropriate software can lower overall latency and increase random performance of drives significantly versus typical SSDs. It is of course too early to say anything about SSDs based on next-generation controllers from Phison, but the partnership between the two companies promises to bring significant performance enhancements to upcoming storage subsystems.

Phison’s SSD partners won't the first to use STT-MRAM as write cache buffers for 3D NAND-based SSDs. Both IBM and Seagate already offer appropriate drives commercially today. Meanwhile, native support of STT-MRAM by SSD controllers will make it considerably cheaper and easier for drive makers to build such products.

Phison and Everspin will discuss use cases of STT-MRAM in enterprise storage applications at Flash Memory Summit in early August.

https://www.anandtech.com/show/14669...ttmram-caching