Stefan Mileschin

Fung Sui for chips

Google boffins have come up with a new way of designing the physical layout of a computer chip.

According to a paper published in the journal Nature, Google researchers applied a deep reinforcement learning approach to chip floorplanning. The result was a new technique that “automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area”.

This means a reinforcement learning method capable of generalising across chips, meaning that it can learn from experience to become both better and faster at placing new chips.

Training AI-driven design systems that generalise across chips is challenging because it requires learning to optimise all possible chip netlists (graphs of circuit components like memory components and standard cells, including logic gates) onto canvases.

The researchers’ system aims to place a “netlist” graph of logic gates, memory, and more onto a chip canvas. The design optimises power, performance, and area (PPA) while adhering to placement density routing congestion constraints. The graphs range in size from millions to billions of nodes grouped in thousands of clusters, and typically, evaluating the target metrics takes from hours to over a day.

https://fudzilla.com/news/pc-hardwar...-floorplanning