jmke

Overall system performance is often marred by the additional chipset latency offset required to run the memory bus and FSB asynchronously. As with Intel chipsets, there are rules that determine just how tRD, memory dividers, and memory CAS (Column Address Strobe) must align to assure that the data transfer between the memory bus and FSB can take place. Users who wish to delve deeper into the technicalities and mathematics of tRD and CAS are encouraged to read this article. Although we are dealing with a different topology here, the concept of data transfer and timing is essentially the same, though additional delays and rules apply when both buses are out of sync with each other.

As there are so many similarities between the 680i and 780i, we'd expect and hope that some of the experience gained over the past 18 months by both NVIDIA and ASUS using the 680i chipset will carry through to the 780i motherboards. Moreover, what does opting for the custom solution from ASUS get you for the extra expenditure over the reference design? Let's take a first look at the ASUS Striker II Formula.

http://www.anandtech.com/mb/showdoc.aspx?i=3267

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