Transmeta Finally Delivers 90nm Chip with Security Caps

jmke · 14th September 2004, 15:48

Transmeta, a designer of low-power microprocessors that are not available widely nowadays, said it finally began to ship its first 90nm commercial chips that feature higher performance, lower power consumption compared to predecessors as well as a feature that enhances security.

“Earlier this month Transmeta began limited production shipments of its second generation Efficeon family of processors, the TM8800 series,” the company said in its statement.

1.60GHz Now, Higher Speeds – in Future

Transmeta’s highly-acclaimed Efficeon processor delivered in mid-October 2003 after some delays is a 256-bit VLIW chip that integrates DDR SDRAM memory and AGP controllers as well as 512KB or 1MB L2 cache depending on its version. It uses special code-morph software to run conventional x86 applications and supports widely-used instruction sets, such as MMX, SSE and SSE2. The Efficeon utilizes 400MHz HyperTransport bus to connect I/O processors.

http://www.xbitlabs.com/news/mobile/...914072659.html

Sidney · 14th September 2004, 16:00

I lost over $100K in stock with this guy. Owned it in year 2000.

It's too much a single country issue: Japan.

14th September 2004, 15:48	#1
jmke Madshrimp Join Date: May 2002 Location: 7090/Belgium Posts: 79,019	Transmeta Finally Delivers 90nm Chip with Security Caps Transmeta, a designer of low-power microprocessors that are not available widely nowadays, said it finally began to ship its first 90nm commercial chips that feature higher performance, lower power consumption compared to predecessors as well as a feature that enhances security. “Earlier this month Transmeta began limited production shipments of its second generation Efficeon family of processors, the TM8800 series,” the company said in its statement. 1.60GHz Now, Higher Speeds – in Future Transmeta’s highly-acclaimed Efficeon processor delivered in mid-October 2003 after some delays is a 256-bit VLIW chip that integrates DDR SDRAM memory and AGP controllers as well as 512KB or 1MB L2 cache depending on its version. It uses special code-morph software to run conventional x86 applications and supports widely-used instruction sets, such as MMX, SSE and SSE2. The Efficeon utilizes 400MHz HyperTransport bus to connect I/O processors. http://www.xbitlabs.com/news/mobile/...914072659.html __________________

14th September 2004, 16:00	#2
Sidney Member Join Date: Mar 2004 Posts: 15,738	I lost over $100K in stock with this guy. Owned it in year 2000. It's too much a single country issue: Japan. __________________ lazyman Opteron 165 (2) @2.85 1.42 vcore AMD Stock HSF + Chill Vent II

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