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Rambus Develops Memory Controller for DDR, DDR2, GDDR, XDR Memory Rambus Develops Memory Controller for DDR, DDR2, GDDR, XDR Memory
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Rambus Develops Memory Controller for DDR, DDR2, GDDR, XDR Memory
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Old 11th May 2004, 01:13   #1
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Default Rambus Develops Memory Controller for DDR, DDR2, GDDR, XDR Memory

Rambus, developer of RDRAM memory that did not manage to become widely used, today unveiled its memory controller that support massively available DDR SDRAM in addition to the thing that has big potential in future – XDR DRAM.

Memory controller from Rambus provides support for mainstream DDR and DDR2 at speeds of up to 800MHz and graphics DDR, including GDDR1, GDDR2, and GDDR3 at up to 1600MHz data rates, Rambus DDR memory controller interface cells are full-featured drop-in physical layer (PHY) cells. The interface cells use proven technology that allow customers to improve time-to-market, minimize design risk and avoid potential re-spin costs. Rambus also offers system engineering services to further accelerate time-to-market, and ensure the interface operates at high frequency in the system environment. Rambus DDR interface solutions are ideal for a broad range of applications, from consumer multimedia and graphics systems to mainstream PCs and servers.

“As DDR memory interfaces become faster and as a result more challenging to design, a growing number of customers are requesting proven solutions,” said Laura Stark, vice president of the Memory Interface Division at Rambus.

Additionally, Rambus is the only company to provide DDR memory controller interfaces with an optional performance mode supporting XDR DRAM, enabling a two-to-eight times increase in system memory bandwidth. Using this capability, customers can develop a single chip that spans multiple price/performance points depending on which memory type is connected.

“By using Rambus DDR solutions for the memory interface, chip designers can focus on other critical portions of the chip. This new solution, along with RDRAM and XDR memory interfaces, rounds out our product portfolio and provides a memory interface for any level of performance need,” Ms Stark added.

Rambus DDR interface circuits are designed for a wide variety of standard CMOS processes, such as 90nm, 0.13 micron and 0.18 micron, and are available immediately on 0.13 micron process. Rambus DDR memory controller interfaces for consumer and graphics applications are available now, and those for main memory applications will be available soon.


http://www.xbitlabs.com/news/memory/...510150050.html
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