Intel talks about Xeon Scalable Processor

Stefan Mileschin · 17th June 2017, 13:23

New mesh speeds access

While Intel has not got around to releasing its Xeon Scalable Processors it is starting to provide a few more details about the Skylake-SP based microarchitecture.

Intel said that a new mesh interconnect architecture has been designed to increase bandwidth between on-chip elements, while simultaneously decreasing latency, and improving power efficiency and scalability.

Writing in his bog, Akhilesh Kimar, Skylake-SP CPU Architect said: “The task of adding more cores and interconnecting them to create a multi-core data center processor may sound simple, but the interconnects between CPU cores, memory hierarchy, and I/O subsystems provide critical pathways among these subsystems necessitating thoughtful architecture. These interconnects are like a well-designed highway with the right number of lanes and ramps at critical places to allow traffic to flow smoothly...”

http://fudzilla.com/news/processors/...able-processor

17th June 2017, 13:23	#1
Stefan Mileschin [M] Reviewer Join Date: May 2010 Location: Romania Posts: 148,597	Intel talks about Xeon Scalable Processor New mesh speeds access While Intel has not got around to releasing its Xeon Scalable Processors it is starting to provide a few more details about the Skylake-SP based microarchitecture. Intel said that a new mesh interconnect architecture has been designed to increase bandwidth between on-chip elements, while simultaneously decreasing latency, and improving power efficiency and scalability. Writing in his bog, Akhilesh Kimar, Skylake-SP CPU Architect said: “The task of adding more cores and interconnecting them to create a multi-core data center processor may sound simple, but the interconnects between CPU cores, memory hierarchy, and I/O subsystems provide critical pathways among these subsystems necessitating thoughtful architecture. These interconnects are like a well-designed highway with the right number of lanes and ramps at critical places to allow traffic to flow smoothly...” http://fudzilla.com/news/processors/...able-processor

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