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Intel Itanium 2 to Get Additional Clock-Speed, Cache Intel Itanium 2 to Get Additional Clock-Speed, Cache
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Intel Itanium 2 to Get Additional Clock-Speed, Cache
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Old 25th May 2004, 15:21   #1
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Default Intel Itanium 2 to Get Additional Clock-Speed, Cache

Intel is on-track with the new flavour of Itanium 2 microprocessor launch in the third quarter this year. The company plans to intro the new flagship IA64 chip at 1.70GHz clock-speed and with 9MB of L3 cache, X-bit labs has learnt.

Madison 9M Hits 1.70GHz

Earlier sources familiar with the roadmap of the world’s largest chipmaker did not reveal the exact core-clock of the forthcoming top-of-the-line chip code-named Madison 9M, restricting themselves with target core-clock range of 1.50GHz to 1.70GHz. The latter is the high-end of Intel’s expectation that reflects the company’s commitment to increasing raw computing power of the IA64 products and also actual ability to commercially ship its 64-bit EPIC microprocessors with large cache and high core-clock speed.

Intel Itanium 2 processors with Madison 9M core are designed for powerful multiprocessor servers and will be available at different clock-speeds with different cache sizes. Intel also has plans to roll-out cut-down version of Madison 9M – code-named Fanwood – for dual-processor servers and workstation. Both Fanwood and Madison 9M will use 400MHz processor system bus and will be drop-in compatible with existing infrastructure, sources said.

Low-Voltage Itanium 2 Gets a Speed Boost

Santa Clara, California-based corporation is currently shipping a number of Itanium 2 flavours for 2-way applications: Itanium 2 1.40GHz with 1.5MB L3 cache, Itanium 2 1.40GHz with 3MB L3 cache, Itanium 2 1.60GHz with 3MB L3 cache as well as Low-Voltage Intel Itanium 2 processor at 1.0GHz with 1.5MB L3 cache, which consumes approximately 62W – half the power of other existing Itanium 2 processors.

Such microprocessors are suitable for technical and scientific computing systems; various clusters; entry-level, front-end enterprise systems as well as network edge and software engineering workstations.

In the Q3 2004 Intel plans to roll-out two more IA64 central processing units to boost its 2P IA64 lineup: Itanium 2 1.60GHz with 3MB L3 cache based on Fanwood core and Low-Voltage Intel Itanium 2 processor at 1.30GHz with 3MB L3. Earlier the company planned to clock the low-voltage revision of the chip at 1.20GHz.

533MHz, 667MHz Processor System Buses for Itanium 2 Ahead

Nowadays high-end Itanium 2 lineup from Intel includes 1.50GHz, 1.40GHz and 1.30GHz models with 6MB, 4MB and 3MB L3 cache respectively. All the current chips use 400MHz Quad Pumped Bus.

667MHz PSB to be introduced early next year will be the first bump for Itanium’s bus speed that is likely to give a strong increase in performance of IA64 multi-processor servers. However, even earlier Intel is expected to boost the PSB clock-rate of Itanium 2 processors designed for 2P servers: in Q4 2004 a cut-down flavour of Madison 9M, chip code-named Fanwood, will get a 533MHz Quad Pumped Bus.

667MHz will be a magic number for Intel processors designed for multi-processor servers. The company’s next-generation Xeon MP processors with Enhanced Memory 64 Technology code-named Potomac will also sport 667MHz processor system bus. The company recently confirmed plans to unify Itanium and Xeon platforms so that both processors would fit into one socket. But the chipmaker does not indicate when exactly this happens.

Multi-core, Dynamic Power Management for Itanium 2 Beyond

Intel officially outlined the long-term Itanium processor roadmap in mid-February 2004, underlining the promise to bring Itanium processors with fabulous performance later during the decade.

Next year will be a big year for Itanium – Intel will launch its first 64-bit multi-core CPUs for high-end servers, something that its competitors – IBM and Sun – have been doing for a while.

Montecito will be Intel’s first IA64 chip with two cores and 24MB of L3 cache. In 2003 Intel uncovered plans to implement its special “arbiter” bus into the chip code-named Montecito to manage how the cores collaborate between themselves, how they utilise their processor system bus and the L3 cache. No actual peculiarities of the design have been presented by Intel officials so far, but we can pre-suppose that the “arbiter” bus architecture may be utilised in all multiple-core CPUs from Intel that will come in future. Millington is a cheaper version of Montecito, probably tailored to serve 2P systems and contain less cache, LV Millington will have lower power consumption compared to the default core.

The Montecito and Millington chips will contain two new technologies: Foxton for dynamic power management and Pellston for correcting data errors in the cache. Intel’s president and COO Paul Otellini recently said that the Foxton is a technology to dynamically boost speed of Itanium 2 chips, but he did not outline, whether this applies to dynamic overclocking or dynamic underclocking. Typically, overclocking is not accepted in mission-critical environments, at the same time, dynamic underclocking can help to reduce power consumption and consequently the cost of ownership.

Tukwila (formerly Tanglewood) will be Intel’s first multi-core IA64 processor with more than two cores. Eventually, there will also be a chip code-named Dimona, a yet another multi-core offspring of the Itanium 2. Both are anticipated for release in 2006 and later.

Official representatives from Intel did not comment on the news-story.
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