Elpida Memory presented technical papers on its two new technologies at the 2004 Symposium on VLSI Circuits, an international conference on integrated circuits held in Honolulu earlier this month. The documents cover technologies aimed to improve performance of DRAM,

The first technology, developed in cooperation with Hitachi, accelerates route-finding in network routers and cache memory applications in servers. The technology incorporates high-speed memory arrays that use two memory cells per bit called “twin-cell memory”, along with a high-speed data amplification method called "three-stage sensing". Based on these technologies, a 144Mb prototype was fabricated and evaluated using Elpida's original 0.11 micron DRAM process for general-purpose DRAM. The prototype achieves exceptional performance with random access time comparable to fast SRAM.

The second new technology developed is a circuit technique for 1Gb DRAM devices that supports both DDR1 and DDR2 on a single chip by combining high speed with high layout efficiency. Incorporated in 1Gb mass-production chips, the technology enables high-speed data rates of 400MHz for DDR1 and 800MHz for DDR2, making it possible to offer large-capacity, high-speed memory for servers and high-end PCs, Elpida said

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