Architecture/Feature Set 102
As we stated the Athlon64 would not use a traditional front side bus. But what did this mean? Why did AMD see fit to replace a working standard with something new? Well the idea was to provide more system bandwidth for this revolutionary CPU design. Whereas cpus have been increasing in performance and frequency according to Moore’s law, system bus and platform speeds have for the most part not kept up with such CPU advances, often becoming the main limiting factor in system performance.
AMD was assimilating a HTT bus, or Hypertransport technology bus to interface the CPU and the motherboard in an effort to remove a prospective barrier to CPU and system performance. The standard was new and developed by AMD and allowed to be open source, in an effort to encourage the standard to flourish. The HTT protocol was more like a Network device than traditional motherboard bus architecture. As David K. Every states in his article, The Hypertransport Revolution
“The current common main bus is a shared, half-duplex bus running at 133MHz and capable of handling 64 bits of data, 8 bytes at a time. Half-duplex means that the processor can talk to memory, and the memory can send back data/results on the same bus, but the instructions can't travel both ways simultaneously.
Hypertransport runs at 800MHz and is "double pumped," meaning data is sent on the upswing and the downswing of the clock, doubling the effective bus speed to 1600MHz.
Hypertransport can use different widths depending on the needs of the bus -- it can be 2, 4, 8, 16 or 32 bits wide. And it is full duplex, so it can send and receive data at the same time. The transmit and receive parts of the bus can be different sizes, depending on needs, but on a main bus, they are likely to be symmetrical. Splitting the transmitting and receiving parts of the bus helps to simplify the design and makes it easier to run the bus at higher speeds.”
Now granted, the bus he describes was a Mac bus, but architectures are similar enough to generalize the benefits. In addition, AMD has jumped up to a 1000 MHz HTT bus which is double pumped and effectively 2000 MHz bringing the potential for performance higher. For reference, AMD’s implementation of HTT for Athlon64 involves 16bit upstream and downstream paths.
So if we do our math correctly and compare platform bandwidth between Intel 800fsb system and AMD Socket 939, we could come up with the following. I’d like to thank Michael Schuette from OCZ for taking the time to explain the equations to me.
Intel system bus- CPU to bus interface=64 bits x 800 MHz fsb effective/8(bit to byte conversion) = 6,400mb/sec (64x800÷8)
AMD Athlon64-cpu to HT interconnect(for 939 chips)=32bit bus(16bit up+16bit down bi-directional full duplex) x 2000mhz effective/8(bit to byte conversion=8,000mb/sec. Now older 754 and Socket 940 chips will run at 1600 MHz bus and will equal 6,400mb/sec bandwidth
The A64 uses HTT to interact with the motherboard. System bus speed and CPU MHz were derived from two equations. At launch the Athlon64 3200+ socket 754 chips ran at 2 GHz and featured 1mb L2 cache. This chip had a 10x multiplier and against a 200 MHz HTT equaled the advertised 2 GHz (10x200 = 2000 MHz) clock speed. The Initial Hypertransport speed supported by the Athlon64 was 800 MHz and since this was a DDR design there was an effective 1600 MHz Hypertransport bus. HTT is one component of total Hypertransport bus speed, but there is also a Hypertransport or LDT (lightning data transport) Multiplier. Default HTT for A64 is 200 MHz. At introduction the A64 supported 800 MHz HTT bus (1600 MHz effective), so therefore boards used a 4x HT/LDT multiplier as math would suggest; 200x4 = 800 MHz.
Easy right? Well not so fast! NVIDIA, one of the chipset makers for initial boards could not get a correctly functional 800 MHz HTT bus stable. So they used a 3x LDT multiplier to limit Hypertransport bus to 600mhz. Labeled the NF3 150 chipset, there was a slight performance penalty when using this board compared with a Via based chipset motherboard based on the KT800 Chipset which allowed a fully functional 800mhz(1600mhz effective) Hypertransport bus.