Stefan Mileschin

Samsung on Monday said that it had developed the industry’s first 12-layer 3D packaging for DRAM products. The technology uses through silicon vias (TSVs) to create high-capacity HBM memory devices for applications that benefit from high memory bandwidth and capacities, such as higher-end graphics, FPGAs, and compute cards.

Samsung’s 12-layer DRAM KGSDs (known good stack die) will feature 60,000 TSV holes which is why the manufacturer considers its technology one of the most challenging packaging for mass production. Despite increase of the number of layers from eight to 12, thickness of the package will remain at 720 microns, so Samsung’s partners will not have to change anything on their side to use the new technology. It does mean that we're seeing DRAM layers getting thinner, with acceptable yields for high-end products.

One of the first products to use Samsung’s 12-layer DRAM packaging technology will be the company’s 24 GB HBM2 KGSDs that will be mass produced shortly. These devices will allow developers of CPUs, GPUs, and FPGAs to install 48 GB or 96 GB of memory in case of 2048 or 4096-bit buses, respectively. It also allows for 12 GB and 6 GB stacks with less dense configurations.

Samsung did not disclose how much will 12-layer 24 GB HBM2 devices cost, but since they will be available exclusively from Samsung, we expect the manufacturer to charge a premium.

https://www.anandtech.com/show/14952...er-3d-tsv-dram