Intel shows PetaFLOPs Scale Xe HP GPU at HotChips

Stefan Mileschin · 19th August 2020, 06:52

4-tile version of the Xe HP GPU

Holding a talk at HotChips 32, Raja Koduri showed a 4-tile Xe HP GPU, the biggest one in the lot, as well as talk about the scalability of the chip.

Aimed at machine learning and AI, the Intel Xe HP GPU, which was previously seen in its smallest, 1-tile configuration back at Intel Architecture Day, now came to HotChips, but in its largest version, 4-tile configuration.

In case you missed it earlier, the Xe HP GPU will be available in 1-tile, 2-tile, and 4-tile configurations, and while we do not have any precise details, Intel did show a scaling demo on how Xe HP GPU scales with peak FP32 hitting 10588 GFLOPs with 1-tile, 21161 GFLOPs in 2-tile, and 41908 GFLOPs in 4-tile configuration, describing it as a chip that brings "the most FP32 performance in a single package".

Unfortunately, we are still missing key architecture and packaging details on how those tiles are connected.

https://fudzilla.com/news/graphics/5...pu-at-hotchips

19th August 2020, 06:52	#1
Stefan Mileschin [M] Reviewer Join Date: May 2010 Location: Romania Posts: 148,797	Intel shows PetaFLOPs Scale Xe HP GPU at HotChips 4-tile version of the Xe HP GPU Holding a talk at HotChips 32, Raja Koduri showed a 4-tile Xe HP GPU, the biggest one in the lot, as well as talk about the scalability of the chip. Aimed at machine learning and AI, the Intel Xe HP GPU, which was previously seen in its smallest, 1-tile configuration back at Intel Architecture Day, now came to HotChips, but in its largest version, 4-tile configuration. In case you missed it earlier, the Xe HP GPU will be available in 1-tile, 2-tile, and 4-tile configurations, and while we do not have any precise details, Intel did show a scaling demo on how Xe HP GPU scales with peak FP32 hitting 10588 GFLOPs with 1-tile, 21161 GFLOPs in 2-tile, and 41908 GFLOPs in 4-tile configuration, describing it as a chip that brings "the most FP32 performance in a single package". Unfortunately, we are still missing key architecture and packaging details on how those tiles are connected. https://fudzilla.com/news/graphics/5...pu-at-hotchips

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