Intel’s Future 7nm FPGAs To Use Foveros 3D Stacking

Stefan Mileschin · 24th August 2020, 09:15

One of the main battlegrounds of future leading-edge semiconductor products will be in the packaging technology: being able to integrate multiple elements of silicon onto the same package with high bandwidth and low power interconnects will be, according to Intel, one way of extending the performance aspects of Moore’s Law into the next decade. Intel has three new parts to its advanced packaging portfolio: EMIB, Foveros, and ODI. At Intel’s Architecture Day 2020, we learned that Intel’s next generation of FPGA products, built on Intel’s own future 7nm manufacturing process, will integrate EMIB from its current generation as well as Foveros 3D stacking.

https://www.anandtech.com/show/16019...os-3d-stacking

24th August 2020, 09:15	#1
Stefan Mileschin [M] Reviewer Join Date: May 2010 Location: Romania Posts: 148,931	Intel’s Future 7nm FPGAs To Use Foveros 3D Stacking One of the main battlegrounds of future leading-edge semiconductor products will be in the packaging technology: being able to integrate multiple elements of silicon onto the same package with high bandwidth and low power interconnects will be, according to Intel, one way of extending the performance aspects of Moore’s Law into the next decade. Intel has three new parts to its advanced packaging portfolio: EMIB, Foveros, and ODI. At Intel’s Architecture Day 2020, we learned that Intel’s next generation of FPGA products, built on Intel’s own future 7nm manufacturing process, will integrate EMIB from its current generation as well as Foveros 3D stacking. https://www.anandtech.com/show/16019...os-3d-stacking

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