AMD Discusses ‘X3D’ Die Stacking and Packaging for Future Products

Stefan Mileschin · 6th March 2020, 12:40

One of AMD’s key messages at its Financial Analyst Day 2020 is that the company wants to remain on the leading edge when it comes to process node technology as well as the latest packaging technology on its newest products. To that end, AMD discussed how it has surged forward with not only 2.5D interposer designs in its GPUs, but also stacked memory and chiplet implementations. The next stage of this journey, according to AMD, is a new X3D die stacking and packaging technology.

The nature of the Financial Analyst Day means that AMD didn’t go into too much detail here, aside from a few diagrams, but the company was clear that it sees its aggressive roadmap for chiplet and 3D integration to lead to this X3D design, where the X stands for ‘hybrid’. AMD’s diagrams show four main compute chiplets, arranged in a 2x2 pattern, and then 4-high stacked die with one per chiplet. All of these chips are then on a large interposer underneath.

https://www.anandtech.com/show/15590...rid-25d-and-3d

6th March 2020, 12:40	#1
Stefan Mileschin [M] Reviewer Join Date: May 2010 Location: Romania Posts: 148,650	AMD Discusses ‘X3D’ Die Stacking and Packaging for Future Products One of AMD’s key messages at its Financial Analyst Day 2020 is that the company wants to remain on the leading edge when it comes to process node technology as well as the latest packaging technology on its newest products. To that end, AMD discussed how it has surged forward with not only 2.5D interposer designs in its GPUs, but also stacked memory and chiplet implementations. The next stage of this journey, according to AMD, is a new X3D die stacking and packaging technology. The nature of the Financial Analyst Day means that AMD didn’t go into too much detail here, aside from a few diagrams, but the company was clear that it sees its aggressive roadmap for chiplet and 3D integration to lead to this X3D design, where the X stands for ‘hybrid’. AMD’s diagrams show four main compute chiplets, arranged in a 2x2 pattern, and then 4-high stacked die with one per chiplet. All of these chips are then on a large interposer underneath. https://www.anandtech.com/show/15590...rid-25d-and-3d

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