3 part Article!
Part I - Part II - Part III
The semiconductor industry's recent motivation to employ SOI (a 30 year-old theory) actually derives from current design changes which force engineers to rethink the MOS, and CMOS transistor all over. As microprocessors are scaled down, and transistors (or micro circuitry) "shrinks" the number of circuits increase in an ever diminutive amount of space. One might surmise a larger number of circuits populating less silicon real-estate would yield prima facie speed increases. However; the opposite is true, in many respects. As the number of transistors increases, so does the wiring, along which voltage travels, thereby increasing the time it takes signals, or voltage to reach a particular destination. Although copper is now implemented, this in itself is not adequate compensation. A more mundane approach was warranted, and SOI literally changes the properties (and topography) of semiconductors substrate around the switches themselves. Manufacturing technologies such as Nan topography, SOI wafer fab, and micro-architecture are now courting heavily, and for good reason soon they will be bedfellows. As the die shrinks, industry-wide manufacturing technologies must grow, and adapt with each advancement. Albeit unforeseen theoretical or real-world effects, all must be considered and must be measured:
For certain SOI manufacturing methods, edge wafer profile control is essential to the bonding process...wafer bonding is very difficult at the edge...have defects in the non-SOI region...Starting silicon parameters of interest include wafer shape, thickness, flatness and Nan topography metrology for both SOI and bulk silicon wafers. Something that is unique to SOI is reflectivity off the BOX layer, which makes thickness measurement very difficult by typical scatterometry methods.
KLA-Tencor (San Jose) developed the NanoPro NP1 tool as a one-stop solution for wafer geometry and Nan topography measurement for SOI and bulk silicon wafers. The system uses grazing incidence angle measurement and proprietary interferometry methods to solve the reflectivity challenges. The tool measures thickness from initial grinding and etching stages of wafer manufacturing to final double-sided polished characteristics. In IC manufacturing, the technology increases stepper throughput by replacing wafer flatness measurements that today are made site-by-site on the stepper.
It's clear the ramifications of the .09 micron architecture, and below will extend well beyond the microchip itself. This begs an industry wide recompense in order to improve equipment used for QC, voltage and other "back-line" related anomalies which can lead to failure. It's obviously not as simple as packing twice as many circuits into a given area, as the technology shrinks, the entire circuitry's electrical behavior changes, as does interaction with the treated silicon. This has given CPU manufacturers a run for their money, literally. As gates become smaller, and voltage drops, capacitance must be reduced, and one must try to curb leakage into other areas of the silicon. Capacitance and leakage become an increasingly difficult challenge. This is where the implementation of SOI wafers is becoming critical:
Silicon-on-insulator (SOI) to protect the chip's millions of transistors with a blanket of insulation, thus reducing electrical leakage. By isolating the individual transistors, SOI allows them to communicate better with each other, and the whole system runs faster. Thus SOI increases performance 20 to 30% over processors that use copper alone...To accommodate exponential growth demands for larger and faster transistor budgets, microprocessor designers constantly push the envelope of technological, physical, and design constraints. SOI can deliver the headroom necessary to continue pushing the envelope for at least the next three to four years. The companies pioneering SOI today consistently find that SOI-based chips improve frequency performance 20 to 35 percent, or diminish power consumption two to three times at the same frequency, relative to bulk CMOS-based processors. In terms of the industry's doubling trend, SOI adoption equates to approximately two years of progress in CMOS technology...Low power dissipation is a key advantage to SOI ...SOI provides a 38 percent improvement in dynamic power and a 46 percent improvement in static power.
Although not named in the quote above, capacitance is evident in every type of electrical switch, otherwise known as the "transistor". Any material which can store electric current has capacitance. A microprocessor is fundamentally a large number of electronic gates, and switches which are either on or off (1 or 0) packed into a silicon substrate. Another term for these silicon/metal switches is MOS (Metal Oxide Semiconductor). In a MOS switch, when high voltage is applied to the metal "gate" the switch closes and current flows. You may also have heard the term CMOS. This is a Complimentary Metal Oxide Semiconductor; in this switch, (which works in a reversal of polarity), when high voltage is applied to the metal gate, the switch opens and current ceases to flow, when low voltage is applied to the gate the switch closes, and current flows, "complimenting" the behavior of the MOS. Both are used in current microprocessor core technology. Albeit a MOS or CMOS, prior to the switches ability to operate, all its internal "capacitance" must be charged. It actually takes longer to charge the switch, and then it does to turn it on and off. In the quote above pertaining to Silicon On Insulator technology, it describes SOI as improving the "communication," via "isolation," and this is crucial element SOI brings to the table. SOI technology places an "Insulator" upon those areas on each side of the gate which, (in prior technologies) having had "impurities" added to them, enable them to conduct charge.
The term "communication" as it is used in the quote above, infers there will be less capacitance, due to the insulation (oxide layer), which insulates static current from leaking into the surrounding silicon. This leakage not only slows the switch down (impairing communication) but static current equates to heat build-up. It's silicon's predilection to be so malleable as to either conduct or insulate electrical current which has made it the material of choice for so long in the semiconductor industry. It also makes it more susceptible to static current, leakage, and electro migration. As microprocessors now fall into the realm of nanotechnology, and the voltages with which they operate have become ever smaller, so new technologies have to be implemented:
With power becoming a severe bottleneck in high-performance nanometer-scale (sub-0.1-micron feature size) IC design, there is a strong need for a cohesive and comprehensive power-aware design methodology...ad hoc approaches are insufficient and inefficient...Beyond traditional static and dynamic power consumption are such further subdivisions as sub threshold and gate leakage components, along with active- and standby-mode leakage. For example, the amount of leakage power in active circuits is a growing concern since it bites off increasingly big chunks of the overall power budget as device geometries shrink... a key example lies in the exponential dependencies of sub threshold leakage on threshold voltage (Vth) and gate leakage on oxide thickness. Because of the small size of MOSFET conducting channels and the small number of dopant atoms therein, the controllability of Vth is becoming more difficult....Deviations on the order of 20 to 30 millivolts can lead to a 100 percent or larger increase in sub threshold leakage, while a reduction in oxide thickness of just 1 angstrom causes gate leakage to more than triple...These dependencies place an incredible burden on process engineers to create controllable processes, leading to rising development costs and turnaround times. In this way, power greatly affects costs.