Tabula Rasa Semantics, in Microprocessor Burn-in. Part-II

CPU by KeithSuppe @ 2003-07-01

Part II of Liquid3D's in-depth research into microprocessor technology, he takes it below zero and kicks it into overdrive!

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The need to control "leakage" has become a monumental task in microprocessor design. There is a very close relationship between "static power," and leakage. Whether the circuit or gate is conducting or in a static state, (holding) it has capacitance, and this is where some leakage will occur regardless of insulation. We are dealing with "semi conductive" material, and its ability to conduct, or insulate, are only as effective as the materials, and their application along the gate's and circuitry where current travels, or remains static. Below is a diagram, exemplifying the difference between SOI silicon, which might be defined as having "latent insulation properties," vs. common gate technology;

Madshrimps (c)

It's evident from the diagram, above the oxide layer, "on" the silicon contains leakage far more effectively then untreated silicon. And where electrons are not contained, they have a propensity for building capacitance, electro migration, and of course adverse thermal effects. Depending upon the effectiveness of the materials employed industry projections which state speed increases of up to 35% seem feasible. If one were to research, explore this topic to its technical finality, (as I've recently begun to do) one would realize this is at the heart of microprocessor design. The best example I can conjure to be the ad hoc extremes to which we must go, to improve a processors performance Liquid Nitrogen. I'm thankful for companies like Chip-Con, who offer the next best alternative, in fact; the only realistic alternative to us as enthusiasts, phase-change. Until SOI, and microprocessor design, can solve capacitance leakage, a Prometeia, is the overclocker, in fact any PC's enthusiasts best bet. Albeit an ad hoc alternative, it will extend the life of the CPU, and allow it run faster, then any other commercially available product. I also want to thank companies such as Thermalright, Vantec, PCPower&Cooling, Maxtor, Corsair, and OCZ. Innovators all, and for their corporate philosophy, I am grateful. One final analogy pertaining to thermal reduction, if you were to itemize the cost of a Cray, you'll find a large percentage is in its cooling system. In fact the term "super-computer" more accurately derives from "super-cooled" computer.

This would be an ideal opportunity to introduce a plethora of technical material, such as pipeline depth, parallelism, secularity, freeze gates, drain, however; the depth, and complexity of such material can fill text-books in post-graduate EE courses, and this article is supposedly for the enthusiast, overclocker, and end-user alike. It will have to suffice, to focus on the key issues of parasitic capacitance, insulation, and thermal dissipation in the following sections. As heat is the Overclockers enemy, so speed is our friend, and the entity responsible for both is current. Regardless of the aging 248nm Lithography process, it was perhaps SOI which had the greatest impact o the .13 micron die shrink, most importantly the isolative properties SOI has upon the wafer's integration of the circuitry. SOI can be thought of as a form of "doping", albeit much more complex in its application. Complications not-with-standing, the .13 micron die size has been an overall success for both Intel, and AMD. In fact Although SOI has been around for quite some time, its attributes will now have the greatest effect upon the performance of .09 micron die shrink, and below. SOI is but one among many manufacturing techniques and changes the semiconductor industry will have to embrace. And there will certainly be controversy among which vehicles will get us to those smaller dies as well. The transition from 248nm lithography to a combination of 248nm and 193nm lithography for the .09 micron process will be quite interesting. The trend towards 300mm diameter wafers, is just as important to manufacturers as any other, as it will certainly be much more cost effective then 200mm.

In so far as SOI, this is (or will be) an industry wide transition, with the exception of Intel, who will utilize SSOI or Strained Silicon On Insulator Fab technology for their wafers. Pertaining to Intel and its adoption of new technologies, there has already been much controversy and economic fallout due to a disagreement between Intel over Lithographic standards. In fact this was the motivation of a vacuous assumption on my part in my last article ( There had been a consortium formed among major semiconductor manufacturers to discuss the implementation of 157nm lithography at the 45-nm node. In an ill-conceived retort to a criticism from an Intel employee, I'd raised the suspicion Intel, in choosing to eschew the 157nm Lithography, had somehow deceived other members of semiconductor industry. The article below was the basis for my accusation.

Intel announced May 23 that it plans to extend 193-nm scanners to the 45-nm node, where the half-pitch actually is about 70 nm. After that, Intel will turn to extreme-ultraviolet lithography (EUV) for the 32-nm node expected at decade's end....Intel's bombshell announcement angered some, who argue that Intel insisted that 157-nm lithography be put back on the industry road map in 1999 as a hedge against EUV's late arrival. These proponents are optimistic that if 157-nm lithography is introduced at the 45-nm node, it may be extended to the 32- and 22-nm nodes with immersion techniques. Development is already under way for the 45-nm node, which moves to volume production in 2007. The half-pitch of the 45-nm node actually is closer to 70 or 75 nm, Silverman noted. The decision means that 193-nm tools will be used for the critical layers of the 90-nm, 65-nm and 45-nm generations at Intel.

Intel's occlusion of 157nm lithography certainly ruffled some feathers among other manufacturers. Still, this is a business foremost, and if Intel can carry the 193nm lithography to 45-nm node, this is the pragmatic choice for Intel. Perhaps other manufacturers should rethink their decision to transition through two costly Lithography re-tools, and take 193nm as far as it can go as well. Considering its immaturity, it's too soon to even judge how far the process may take core die-shrinks? It does have vaguely nefarious implications if ones imagination is to go there. Picture the semiconductor "Families" sitting around the technology table, as the "godfather" Intel, makes them an offer they can't refuse. Of course, Intel then refused it? I would think very few companies could be so blatantly deceptive. Then again when I learned Kwok Yuen Ho and Betty Ho of ATI, along with five of the top executives, "inside traded" 494,000 shares of their own ATI stock, and were in front of the Ontaro Securities Commission this February, is anything so implausible? The ATI indiscretion occurred just prior to their Q3/2000 earnings report, which was to show lower then expected earnings for ATI, and they saved (at the expense of share-holders) approximately seven million dollars on the sale. (Statement of Allegations by OSC)

Sure these are two "different" and distinct companies, however Intel has had its improprieties. Regardless, this in not an Inquirer article. I only wanted to touch on my indiscretion, and make amends. I digress. This article is not merely a retraction or amendment of my earlier assertions in the "TBread, Ingots" piece, but to focus primarily on the current evolution in "Fab" technology, and microprocessor design.
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