TSMCs 40nm is actually 45nm
 

Got that? Up until a few weeks ago, Altera thought it was working on a 45nm process. Until someone at TSMC decided that they were better off calling it a 40nm process. It's no big surprise, because the people talking about the self-same process at the International Electron Device Meeting (IEDM) last December also thought of it as a 45nm process. Which kind of makes you wonder just what TSMC claimed to be shipping last autumn when the company said it had shipped 45nm-process wafers to lead customers.

The issue of what constitutes a process node is something that has exercised Kevin Gibb of Chipworks, the Canadian electronics-analysis company. The number we have been using to describe a process node has pretty much lost all meaning. I have to agree with him, as well as Kaizad Mistry of Intel, who said in his talk about Intel's 45nm process at IEDM: "Contacted gate pitch is perhaps the most important [design] rule for density.”

Once upon a time, the number associated with a given process meant how long the transistor gate was. Then, thanks to some optical trickery, everybody worked out that they could reduce the size of the gate, and increase the speed of circuits, by much more than traditional scaling rules. The result was that, by the time the industry hit 90nm, gates were down to less than 60nm in length. At 65nm, you could find devices with gates not much longer than 40nm.

http://blog.hackingcough.com/2008/04...-5nm-diffe.htm