TSMC's SRAM scaling slows
 

Chip price hikes expected

TSMC's SRAM Scaling has slowed tremendously and while new fabrication nodes are expected to increase performance, cut down power consumption, and increase transistor density prices are likely to rise.

According to WikiChip, circuits have been scaling well with the recent process technologies, but SRAM cells have been lagging behind and ran out of steam when TSMC bought in its 3nm-class production nodes.

When TSMC formally introduced its N3 fabrication technologies earlier this year, it said that the new nodes would provide 1.6x and 1.7x improvements in logic density when compared to its N5 (5nm-class) process.

However, it forgot that SRAM cells of the new technologies almost do not scale compared to N5. A TSMC paper published at the International Electron Devices Meeting (IEDM) said that TSMC's N3 features an SRAM bitcell size of 0.0199µm^², which is only ~5% smaller compared to N5's 0.021 µm^²SRAM bitcell.

This gets worse with the revamped N3E as it comes with a 0.021 µm^² SRAM bitcell (which roughly translates to 31.8 Mib/mm^²), which means no scaling compared to N5.

Intel's Intel 4 (7nm EUV) reduces SRAM bitcell size to 0.024µm^² from 0.0312µm^² while Intel 7 (formerly known as 10nm Enhanced SuperFin) manages 27.8 Mib/mm^², which is a bit behind TSMC's HD SRAM density.

https://fudzilla.com/news/pc-hardwar...-scaling-slows