Synopsys and TSMC Collaborate for 20 nm Reference Flow
 

Synopsys, Inc., a global leader accelerating innovation in the design, verification and manufacture of chips and systems, today announced 20-nanometer (nm) process technology support for the TSMC 20 nm Reference flow. This includes Synopsys Galaxy Implementation Platform support for the latest TSMC 20 nm design rules and models. The collaboration between TSMC and Synopsys on 20nm technology allows designers to gain performance, power efficiency and chip density advantages while achieving predictable design closure with the industry-proven Synopsys RTL to GDSII solution.

TSMC's 20 nm Reference Flow addresses 20 nm design challenges with a transparent double patterning aware design flow enabling double patterning technology (DPT) compliance, pre-coloring capability, new RC extraction methodology, DPT sign-off, and integrated design-for-manufacturing (DFM). The new Reference Flow's transparent DPT enablement reduces DPT design complexity, achieves required accuracy, minimizes 20 nm design flow setup and learning curve, and accelerates 20 nm process adoption.

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