jmke

Each series of coprocessors unveiled by the company uses the standard HyperTransport (HT) interface to communicate with the main processor. The low end coprocessor, the DRC100-L60ES, uses a 200MHz by 8-bit HT link. DRC's two high end modules, the DRC100-L60 and the DRC110-L160 both use a 400MHz by 16-bit interface instead. DRC coprocessors range in size from 50,000 to 140,000 programmable gates and all three can utilize 6.4GBps between the Xilinx FPGA and the DDR400 memory bank.

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