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Memory Makers Plan for Terabit Memory Using 3D Packaging Memory Makers Plan for Terabit Memory Using 3D Packaging
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Memory Makers Plan for Terabit Memory Using 3D Packaging
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Old 20th December 2006, 14:09   #1
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Default Memory Makers Plan for Terabit Memory Using 3D Packaging

NEC Electronics, working jointly with Elpida Memory and Oki Electric, says it has developed novel packaging technology that places eight memory chips and one controller chip in a vertical stack, with 3D connections between the chips.

The key feature of the new technology is the way that chips in the stack are connected. Each chip has more than 1,000 pins on each side. The pins are connected to polysilicon electrodes built into the chips themselves, vertically piercing the chips from top to bottom. The chips are then connected to each other by high-density microbumps spaced only 50 micrometers apart. The entire package, including the controller chip, is very compact because each of the eight memory chips is only 50 micrometers thick.

http://www.dailytech.com/article.aspx?newsid=5408
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