‘Better Yield on 5nm than 7nm’: TSMC Update on Defect Rates for N5
 

One of the key metrics on how well a semiconductor process is developing is looking at its quantitative chip yield – or rather, its defect density. A manufacturing process that has fewer defects per given unit area will produce more known good silicon than one that has more defects, and the goal of any foundry process is to minimize that defect rate over time. This will give the customers better throughput when making orders, and the foundry aims to balance that with the cost of improving the manufacturing process.

https://www.anandtech.com/show/16028...t-rates-for-n5