AMD explains how it mixes nodes to gain efficiency
 

First, break three eggs

AMD has been explaining how it has been squeezing out improved performance from its latest chips.

According to Toms Hardware AMD said that Zen 4 uses three nodes: the 5 nm node for the CCD, the 6 nm node for the IO die, and the 7 nm node for the V-Cache.

The V-Cache sits over the middle of the CCD, and the eight cores flank the sides.

This apparently caused the outfit some difficulties when it stacked one node onto another during its recent ISSCC presentation. Both the 7950X3D and the original 5800X3D have their V-Caches positioned over their regular L3 caches to allow them to be connected. The arrangement keeps the V-Cache away from the heat produced by the cores. While the V-Cache fits over the L3 cache in the 5800X3D, it overlaps with the L2 caches on the edges of the cores in the 7950X3D.

https://fudzilla.com/news/pc-hardwar...ain-efficiency