AMD details ThreadRipper, Epyc processors
 

At today's press conference, AMD has confirmed that the 16 core processor will for most purposes be half of an Epyc processor. This means that the two die MCM chip will feature 4 DDR4 channels and a whopping 64 lanes of PCIe, with all 64 lanes being enabled for all ThreadRipper SKUs. This will be broken up into 60+4: 60 lanes directly from the CPU for feeding PCIe and M.2 slots, and then another 4 lanes going to the chipset (with an undisclosed number of lanes then coming off of it) to drive basic I/O, USB, and other features. AMD seems to be particularly relishing the point on PCIe lanes in light of the yesterday's Intel HEDT announcement, which maxes out at 44 lanes and no chip below $1000 actually has all of them enabled. All this competition.

http://osnews.com/story/29842/AMD_de...pyc_processors