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|4th January 2004, 16:42||#21|
One more little question regarding a P4 setup:
I have 2*256 pc3200 ram running with a p4 2.6c
it currently runs smooth @231Fsb BUT! it is on a 5/4 divider, so the memory runs only @ 180fsb, however: when i place it higher for exampe on 240/190 something craps out immediately, is it the cheap ram? or a crappy p4c? mobo is Richbastards p4p800vm which ran over 300fsb so that shouldn't be a problem
PSU is only 365watt however...
|4th January 2004, 21:56||#25|
i hope that these are not silly questions but i am curious how many times these tests were run? are these scores based on one run? or multiple runs with the final results just an average score? also, is there any conclusion given as to why 2-2-2-11 would run faster? and, would it be safe to assume that 2-2-2-11 would be faster on ANY nforce2 mtb? or it only pertains specifically to just for the one that was used in these tests?
|4th January 2004, 22:08||#26|
I have a question What happens when you try and overlclock two memmory sticks with diffrent FSB like some 2100 and 2700? How about overclocking with two sticks in Dual Channel mode? How identicle do the sticks have to be? Is there anyway to overclock two sticks seperately?
|4th January 2004, 22:12||#27|
hello persons who are unregistred,plz make the time to register,its free and then your a member here with much more options
unregistred numver one: i've tested 223fsb 2 2 2 5 (dcddr) and 223fsb 2 2 2 11 multiple times with sisoft(synthetic bench),it gave me a increase!,i dontknow of real time noticable difference though...
unregistred number two:
you can go dcddr with your two sticks of ram,but your fsb will be limited with what ur pc2100 can do!
|4th January 2004, 23:23||#29|
Join Date: May 2002
|5th January 2004, 03:11||#30|
2-2-2-5 is a b.s. setting according to Mushkin. Should be 2-2-2-6, wonder if that's why the performance is degraded vs. 11? You think?
"Now imagine someone closes the book you are reading from in the middle of a sentence. Right in your face! And does it over and again. This is what happens if tRAS is set too short. So here is the really simple calculation: The second burst of four has at least to be initiated and prefetched into the output buffers (like you get a glimpse at the headline in a book) before you can close the page without losing all information. That means that the minimum tRAS would be tRCD+CAS latency + 2 cycles (to output the first burst of four and make way for the second burst in the output buffers)."
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