Why the initial desktop Sandy Bridge-E chips has only six (of eight) cores enabled?
 

We all know the Sandy Bridge E die has a total of 8 cores and 20 MB L3 cache, in addition to dual QPI links and quad DDR3 memory channels. Since the Xeon E5 workstation and server parts will have all of them, why are the desktop ones left with only six cores and 15 MB L3 cache? Look at the TDP (thermal design power) for an answer...

http://vr-zone.com/articles/why-the-...ed-/13748.html