Intel to move to common CPU architecture
IDF — Intel CEO Paul Otellini announced today in his keynote address at the Intel Developer Forum that Intel will be moving its future CPUs to a common architecture. He said the architecture will incorporate the best of the current Netburst and mobile architectures, with a focus on delivering more performance per watt. The architecture will be used in mobile platforms (code-named Merom), desktops (Conroe), and servers (Woodcrest). This processor architecture will feature a range of next-generation Intel technologies, including 64-bit compatibility (EM64T), virtualization (VT), Intel's LaGrande security features, and Intel Active Management Tech (iAMT).
These CPUs are dual-core products built on Intel's 65nm process technology, and Otellini presented live demos of all three processors running various operating systems. Otellini's presentation was driven by a Merom-based laptop. He showed Linux running on the desktop-targeted Conroe chip and Windows Server 2003 on Woodcrest. Otellini said the silicon is already "running quite well," and the company expects to ship products in the second half of 2006.
Otellini said Conroe should deliver five times the performance per watt of the Netburst microarchitecture in desktop platforms.
Before this new architecture debuts, Intel will still deliver its first generation of 65nm processsors for mobile (Yonah), desktops (Presler), and servers (Dempsey) in the first half of 2006.
Unfortunately, Otellini's address has so far been short on nitty-gritty details of the new architecture, such as the possible integration of a memory controller, changes to bus technology, or microarchtectural innovations. We will be hunting for additional details and reporting them back to you as they become available.
Everybody is awake now.
in that department A64 is way ahead:)
Yeap, everybody is trying to solve Intel's problem (heat), except Intel. Now Intel sets a new standard "performance per watt".
The title should have been "Intel moves to better use of common sense".
The new architecture behind Merom, Conroe and Woodcrest contains a number of technological enhancements, but it also harks back to earlier designs. The chips will have a 14-stage pipeline, said Steve Smith, vice president of the Digital Enterprise Group. The pipeline is like a chip's assembly line. More stages allow a chip to run at faster speeds, but also mean greater power consumption.
While earlier Pentium III and II chips had similar-size pipelines, the Pentium 4 had a 20-stage pipeline when it debuted and a bloated 31 stages in later chips. Many analysts blamed the power consumption problems in the Pentium 4 in part on the long pipeline.
The chips will also not include hyperthreading, which lets a single core perform more than one task at once, to cut power consumption, said Smith. He added, however, that threading may be added in future versions of chips based on this architecture.
Smith also said that the cores on these chips will share a single cache, similar to IBM's Power 4 dual-core chips. AMD's and Intel's current dual-core chips have separate caches.
Additionally, the chips will come with an improved out-of-order execution unit, which improves performance by allowing a chip to complete tasks without having to wait until other calculations are complete.
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