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Cadence Announces Tapeout of 14 nm Test-Chip Cadence Announces Tapeout of 14 nm Test-Chip
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Cadence Announces Tapeout of 14 nm Test-Chip
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Old 31st October 2012, 06:42   #1
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Default Cadence Announces Tapeout of 14 nm Test-Chip

Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today the tapeout of a 14-nanometer test-chip featuring an ARM Cortex-M0 processor implemented using IBM's FinFET process technology. The successful tapeout is the result of close collaboration between the three technology leaders as they teamed to build an ecosystem to address the new challenges from design through manufacturing inherent in a 14-nanometer FinFET-based design flow.

The 14-nanometer ecosystem and chip are significant milestones of a multi-year agreement between ARM, Cadence and IBM to develop systems-on-chip (SoCs) at the advanced process nodes of 14 nanometers and beyond. SoCs designed at 14 nanometers with FinFET technology offer the promise of a significant reduction in power consumption.
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