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|17th September 2003, 22:42||#1|
Overclocking basics 101
General Overclocking Steps
This is a possible method to overclock a new CPU.
Update your Bios to the newest.
a) PCI locked Motherboard: lock agp/pci to "fixed", 66/33
b) not PCI locked: Use the PCI/AGP divider to regulate the PCI. The PCI bus should not exceed 38Mhz. If it does, you will either suffer from instability problems or you will run the risk of corrupting the data on your hard drive. Ex. If you have a motherboard with a 1/5 PCI/AGP divider you do not want to exceed 190 Mhz FSB since 190/5 = 38 Mhz.
Begin to raise the FSB by increments of 5 Mhz and test it with Prime95 and memtest86 until the machine becomes unstable. By unstable it creates rounding error in Prime95 or errors in memtest86. When the computer gets to be unstable with a high FSB, back it down slowly (2Mhz at a time) until the computer regains its stability with Prime95 and memtest86.
Or try 2 x SuperPi to the 2M digit and 1 full benchmark of 3DMark2001SE on default settings (CooLJoE - System)
Change your DRAM frequency: try 3:2 divider first, then 5:4. Set DDR Voltage to 2.80 (increase only if the system is unstable +0.025 at a time.)
Test with Prime95 and 3D Mark 2001 (loop for 45min - 2hrs) if your system is stable. You will know it is unstable when Prime95 encounters a rounding error (or any error of that sort) or if 3DMark2001 dumps you back to the desktop in the middle of a benchmark.
To see if you can get more out of the CPU begin to raise the CPU's voltage, but do not go over 1.70v otherwise you will damage your CPU. Try 1.535 first, then go up +0.025 at a time.
Set Performance Mode: PAT to "Turbo" or "Ultra"
Set CPU Config: Hyperthreading Technology to "on"
Set Chipset: Performance Acceleration Mode to "on"
Tweak Your RAM in BIOS
Automatic Configuration (DRAM Auto, Timing Selectable, Timing Configuring)
--> set OFF
Nathan recommend to set 3-8-4-4
CAS Latency tCL (CAS Latency Time, CAS Timing Delay): 3
RAS-to-CAS Delay tRCD (RAS to CAS Delay, Active to CMD): 8
RAS Precharge Time tRP (RAS Precharge, Precharge to active): 4
Row Active Time tRAS (Active to Precharge Delay, Precharge Wait State, Row Active Delay, Row Precharge Delay): 4
Bank Interleaving (Bank Interleave)
Options: Off/ 2/ 4
--> set 4
Option: 4/ 8
--> set 8
Command Rate CMD (Command Rate, MA 1T/2T Select)
Options: 1/ 2
--> set 1
Final test: Check your system with Prime95 and other benchmark programs if your system is stable. The temparture of your system should not exceed 50 C °, otherwise you need a better cooling system. IC7 temps tend to be 10-15 degrees higher, so i just subtract 10 from what the windbond hardware doctor shows as your current CPU temperature.
Step 10 Optional
Overclock your graphics card and if you have use Raid 0.
Example by Nathan
Settings for maximum overclock: (With PC3200 Ram)
Memory Timings 3-8-4-4
Cpu Voltage 1.65
Memory Voltage: 2.8
Memory Divider: 3/2
If you want to manually configure your memory timings, you will have to deactivate the automatic RAM configuration.
Specifies the clock speed of the memory bus. This rate is normally specified relative to the front-side bus clock. DDR technology (double-data rate) doubles the data rate given by the actual bus clock speed.
CAS Latency tCL (CAS Latency Time, CAS Timing Delay):
The number of clock cycles that pass from the column being addressed to the data arriving in the output register. The memory manufacturer lists the best possible setting as the CL rating.
RAS-to-CAS Delay tRCD (RAS to CAS Delay, Active to CMD):
Number of clock cycles that pass between the row address being determined and the column address being sent out. Setting this value to two clock cycles can enhance performance by up to four percent.
RAS Precharge Time tRP (RAS Precharge, Precharge to active):
Number of clock cycles needed to precharge the circuits so that the row address can be determined.
Row Active Time tRAS (Active to Precharge Delay, Precharge Wait State, Row Active Delay, Row Precharge Delay):
Delay that results when two different rows in a memory chip are addressed one after another.
DDR RAM memory chips are made of four banks. Addressing all four banks through interleaving at the same time will maximize your performance.
The burst length specifies how many data blocks are sent in one transmission cycle. Ideally, one transmission will fill one memory row on the L2 cache found in modern Pentium 4 and Athlon XP CPUs. That is equal to 64 Bytes, or eight data packets.
Command Rate CMD:
Number of clock cycles needed to address the memory module and the memory chip with the desired data zone. If your memory banks are full to capacity, you will have to raise this rate to two, resulting in a considerable drop in performance.
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