Don't you love the brilliance of it (and MM) :D

If Intel increases the cpu-uncore interconnect to 192-bit, even an 8-core design is possible without too much trouble :)

The question now is where the limitation is of the Nehalem architecture. I still have to read up on how the data is arranged in cpu/cache to figure out in what way the current design can be modified.

If anyone has a link that points to an article explaining data arrangement, please post.

all way to technecal for me :D.
im more cavemen, stick and stone if that wont help: its MC Hammer time.

Couldn't be bothered to make a fine, nice drawing in paint, so just took a picture of the whiteboard as I need to clean it for something new. Sorry for the gigantic picture.

archive it here, no probs; pic looks tiny on 24" ;)

I have a large version, but can't upload it to [M]-threads as it's 2000x1750

yes, but there's no need for exaggeration ;) I also have 12Mpixel shots:p

sweet stuf to read man