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13th November 2009, 21:06 | #21 |
[M] Reviewer Join Date: Sep 2005
Posts: 1,887
| Don't you love the brilliance of it (and MM) |
13th November 2009, 21:17 | #22 |
[M] Reviewer Join Date: Nov 2004 Location: Waregem
Posts: 6,466
| If Intel increases the cpu-uncore interconnect to 192-bit, even an 8-core design is possible without too much trouble |
14th November 2009, 11:56 | #23 |
[M] Reviewer Join Date: Nov 2004 Location: Waregem
Posts: 6,466
| The question now is where the limitation is of the Nehalem architecture. I still have to read up on how the data is arranged in cpu/cache to figure out in what way the current design can be modified. If anyone has a link that points to an article explaining data arrangement, please post. |
14th November 2009, 13:45 | #24 |
Member Join Date: Apr 2005
Posts: 1,338
| all way to technecal for me . im more cavemen, stick and stone if that wont help: its MC Hammer time.
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19th November 2009, 17:04 | #25 |
[M] Reviewer Join Date: Nov 2004 Location: Waregem
Posts: 6,466
| |
19th November 2009, 17:34 | #26 |
Madshrimp Join Date: May 2002 Location: 7090/Belgium
Posts: 79,021
| archive it here, no probs; pic looks tiny on 24"
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19th November 2009, 17:42 | #27 |
[M] Reviewer Join Date: Nov 2004 Location: Waregem
Posts: 6,466
| I have a large version, but can't upload it to [M]-threads as it's 2000x1750 |
19th November 2009, 17:50 | #28 |
Madshrimp Join Date: May 2002 Location: 7090/Belgium
Posts: 79,021
| yes, but there's no need for exaggeration I also have 12Mpixel shots
__________________ |
19th November 2009, 17:58 | #29 |
Member Join Date: Aug 2008 Location: Belguim => Zulte
Posts: 221
| sweet stuf to read man |
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