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@ 2010/11/25At the International Solid-State Circuits Conference (ISSCC) 2011 Advanced Micro Devices plans to reveal additional details about its code-named Bulldozer micro-architecture as well as implementations of forthcoming microprocessors on its base. Apparently, AMD's next-gen chips will be capable of working at over 3.50GHz, which is a quite high-speed, considering the fact that the central processing units (CPUs) will have up to eight cores.
During an ISSCC session on the 21st of February, AMD will describe its dual-core processor module of eight-core Bulldozer microprocessor, according to the agenda on the web-site of the conference. During another session on the 22nd of February the company will describe implementation of its 8MB unified level-three cache of Bulldozer microprocessors. The presentations will be dedicated to ways of reducing die size, power consumption as well as improvements of yields. The description of the sessions shed more light onto the characteristics of AMD's implementation of Bulldozer micro-architecture on 32nm silicon-on-insulator process technology, which is known as code-named Orochi design (Zambezi is desktop version, Valencia is server version).
During an ISSCC session on the 21st of February, AMD will describe its dual-core processor module of eight-core Bulldozer microprocessor, according to the agenda on the web-site of the conference. During another session on the 22nd of February the company will describe implementation of its 8MB unified level-three cache of Bulldozer microprocessors. The presentations will be dedicated to ways of reducing die size, power consumption as well as improvements of yields. The description of the sessions shed more light onto the characteristics of AMD's implementation of Bulldozer micro-architecture on 32nm silicon-on-insulator process technology, which is known as code-named Orochi design (Zambezi is desktop version, Valencia is server version).
