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@ 2004/08/28PALO ALTO, Calif.--The dual-core chips that Advanced Micro Devices and Intel plan to bring to market next year won't be sharing their memories.
A version of Opteron coming in 2005 and Montecito, a future member of Intel's Itanium family also slated for next year, will both have two processor cores, the actual unit inside a processor that performs the calculations, and each core will have separate caches, pools of memory integrated into the chip for rapid data access, according to company presentations at the Hot Chips conference at Stanford University.
Each core of Montecito, for instance, will come with a 1MB level two cache and a 12MB level three cache, according to Cameron McNairy, a researcher at Intel. To date, Intel has mostly said that Montecito's level 3 cache will contain 24MB of memory.
Similarly, each core of the dual-core Opteron will have separate caches, said Marius Evers, a researcher at AMD. Putting two cores on one chip increases computing performance while controlling power consumption, a major problem facing designers.
Splitting the cache differs from the approach taken by IBM, which came out with the first dual-core server chip with the Power 4, according to Kevin Krewell, editor in chief of the Microprocessor Report.
Keeping the cache as one single unit theoretically allows each processor core to access more data in a rapid fashion. Dividing the cache, however, also cuts down on some design work.
"Under time pressure, it is the easiest way for these guys," Krewell said. Later, they may unify the caches. Sun is taking a similar approach with the dual-core UltraSparc IV, he added.
Intel will likely flesh out its dual-core chip strategy at the Intel Developer Forum, which takes place in San Francisco in September. Along with Montecito, Intel will come out with a dual-core chip for desktops in the second half of 2005.
Other IDF highlights include the release of an Itanium 2 with 9MB of cache, according to sources.
AMD, meanwhile, will detail its dual-core plans at the Microprocessor Forum starting Oct. 5 in San Jose, according to the conference program. AMD's dual-core chips are due in the second half of 2005 as well.
Speaking of the Microprocessor Forum, Krewell said the sponsoring organization will not be handing out its trademark portfolio that contains chips highlighted at the conference embedded in the portfolio cover. Companies no longer give samples out, Krewell explained.
A version of Opteron coming in 2005 and Montecito, a future member of Intel's Itanium family also slated for next year, will both have two processor cores, the actual unit inside a processor that performs the calculations, and each core will have separate caches, pools of memory integrated into the chip for rapid data access, according to company presentations at the Hot Chips conference at Stanford University.
Each core of Montecito, for instance, will come with a 1MB level two cache and a 12MB level three cache, according to Cameron McNairy, a researcher at Intel. To date, Intel has mostly said that Montecito's level 3 cache will contain 24MB of memory.
Similarly, each core of the dual-core Opteron will have separate caches, said Marius Evers, a researcher at AMD. Putting two cores on one chip increases computing performance while controlling power consumption, a major problem facing designers.
Splitting the cache differs from the approach taken by IBM, which came out with the first dual-core server chip with the Power 4, according to Kevin Krewell, editor in chief of the Microprocessor Report.
Keeping the cache as one single unit theoretically allows each processor core to access more data in a rapid fashion. Dividing the cache, however, also cuts down on some design work.
"Under time pressure, it is the easiest way for these guys," Krewell said. Later, they may unify the caches. Sun is taking a similar approach with the dual-core UltraSparc IV, he added.
Intel will likely flesh out its dual-core chip strategy at the Intel Developer Forum, which takes place in San Francisco in September. Along with Montecito, Intel will come out with a dual-core chip for desktops in the second half of 2005.
Other IDF highlights include the release of an Itanium 2 with 9MB of cache, according to sources.
AMD, meanwhile, will detail its dual-core plans at the Microprocessor Forum starting Oct. 5 in San Jose, according to the conference program. AMD's dual-core chips are due in the second half of 2005 as well.
Speaking of the Microprocessor Forum, Krewell said the sponsoring organization will not be handing out its trademark portfolio that contains chips highlighted at the conference embedded in the portfolio cover. Companies no longer give samples out, Krewell explained.
