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@ 2010/09/24The eight-core microprocessors from Advanced Micro Devices based on the Bulldozer micro-architecture that feature Orochi design will get massive internal cache systems compared to current-generation of chips. In total, the top-of-the-range single-die processor will have 16MB of cache.
AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.
AMD Orochi chip (which is a universal server and client design that will power Valencia, Zambezi and possibly other implementations of first-gen Bulldozer family) will have 8MB unified level-three cache, according to a document seen by X-bit labs. Since eight-core Orochi features four dual-core Bulldozer modules, each of which is believed to have 2MB of shared level-two cache, the whole chip will pack in whopping 16MB of SRAM, a 77% increase from the current six-core microprocessors that have 9MB of cache in total.
