Intel Core 2: The effect of memory timings

It seems that memory timings do make a little bit of difference, but not as much as we were expecting, in all honesty. We think that a lot of this is down to the fact that Intel's Israeli design team managed to architect an incredibly efficient way of reducing memory accesses. Both cores can share the same L2 cache meaning that the two cores can share one copy of the data and it also eliminates the need for cache coherency traffic to be passed through the memory controller, reducing traffic going across the front side bus.