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Follow us on FacebookKioxia and Western Digital announce 218-layer 3D NAND
@ 2023/04/031Tb TLC and QLC flash chips
Kioxia Corporation and Western Digital Corp., have both announced today details of their newest 3D flash memory technology, the 218-layer 3D NAND with 1Tb TLC and QLC chips.
According to provided details, companies have applied advanced scaling and wafer bonding technologies in order to achieve higher capacity, performance, and reliability, all while keeping the cost down, making it "ideal for meeting the needs of exponential growth across a broad range of market segments."
Companies are using a balance between vertical and lateral scaling in order to come up with greater capacity in a smaller die with fewer layers, at an optimized cost. They use the CBA (CMOS directly Bonded to Array) technology, which means that each CMOS wafer and cell array wafer is manufactured separately, and then bonded together.
The new 218-layer 3D flash uses 1Tb triple-level-cell (TLC) and quad-level-cell (QLC) with four planes with innovative lateral shrink technology which increased bit density by 50 percent. With high-speed NAND I/O reaching 3.2Gb/s, which in a 60 percent improvement over the previous generation, combined with a 20 percent write performance and read latency improvement, lead to higher overall performance and usability for users, according to statements.
Kioxia Corporation and Western Digital Corp., have both announced today details of their newest 3D flash memory technology, the 218-layer 3D NAND with 1Tb TLC and QLC chips.
According to provided details, companies have applied advanced scaling and wafer bonding technologies in order to achieve higher capacity, performance, and reliability, all while keeping the cost down, making it "ideal for meeting the needs of exponential growth across a broad range of market segments."
Companies are using a balance between vertical and lateral scaling in order to come up with greater capacity in a smaller die with fewer layers, at an optimized cost. They use the CBA (CMOS directly Bonded to Array) technology, which means that each CMOS wafer and cell array wafer is manufactured separately, and then bonded together.
The new 218-layer 3D flash uses 1Tb triple-level-cell (TLC) and quad-level-cell (QLC) with four planes with innovative lateral shrink technology which increased bit density by 50 percent. With high-speed NAND I/O reaching 3.2Gb/s, which in a 60 percent improvement over the previous generation, combined with a 20 percent write performance and read latency improvement, lead to higher overall performance and usability for users, according to statements.
