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@ 2005/11/27After using 800MHz processor system bus (PSB) for years, Intel Corp. is now expected to release chips for servers that feature busses clocked at 1066MHz and 1333MHz next year, the company revealed recently. Higher speed busses will be available on processors that use Intel’s next-generation micro-architecture, it indicated.
Jason Waxman, director of server platforms group at Intel Corp., recently announced that the company’s code-named Woodcrest processor, which is a successor of Intel’s Xeon DP chip produced using 65nm code-named Dempsey, will have 1333MHz processor system bus and core-logic to support the chip will be able to handle two of such busses. Such technology is called dual independent bus (DIB) and is also to be supported on Intel’s code-named Blackford chipset that will be able to work with two dual-core Dempsey processors using independent PSBs.
Intel’s code-named Woodcrest dual-core processors are slated to be shipped in the second half of 2006, according to Intel’s roadmap.
Given that Intel’s server processors typically utilize technologies that are also used on desktops or were previously used on desktops, it is highly likely that Intel’s forthcoming desktop chips that are to be available in 2006 will support 1333MHz Quad Pumped Bus. With higher speed busses Intel's server processors are likely to offer much higher performance levels compared to what is available now, which will add pressure on rival Advanced Micro Devices.
Earlier this year Intel confirmed that processors code-named Merom, Conroe and Woodcrest would not be based on the NetBurst architecture that powers current Intel Pentium 4 and Intel Xeon chips. Besides new architecture, which is expected to feature shorter pipeline and high performance per clock, the chips will also sport capabilities like virtualization capabilities, LaGrande technology, 64-bit capability in addition to EDB, EIST and iAMT2.
The code-named Merom processor will feature 14-stages pipeline, down from 31 or more stages found in current Intel Pentium (Prescott) designs, 4-issue out-of-order execution engine as well as improved performance of the floating-point unit (FPU). This greatly showcases the substantial difference from the current NetBurst chips that have very deep pipeline and cannot boast with really high-performance FPUs. Furthermore, 14-stages pipeline is deeper compared to AMD Athlon 64’s 12-stages pipeline, which, on the one hand, allows slightly higher clock-speeds compared to the AMD64 architecture, but, on the other hand, may mean a bit lower efficiency.
Jason Waxman, director of server platforms group at Intel Corp., recently announced that the company’s code-named Woodcrest processor, which is a successor of Intel’s Xeon DP chip produced using 65nm code-named Dempsey, will have 1333MHz processor system bus and core-logic to support the chip will be able to handle two of such busses. Such technology is called dual independent bus (DIB) and is also to be supported on Intel’s code-named Blackford chipset that will be able to work with two dual-core Dempsey processors using independent PSBs.
Intel’s code-named Woodcrest dual-core processors are slated to be shipped in the second half of 2006, according to Intel’s roadmap.
Given that Intel’s server processors typically utilize technologies that are also used on desktops or were previously used on desktops, it is highly likely that Intel’s forthcoming desktop chips that are to be available in 2006 will support 1333MHz Quad Pumped Bus. With higher speed busses Intel's server processors are likely to offer much higher performance levels compared to what is available now, which will add pressure on rival Advanced Micro Devices.
Earlier this year Intel confirmed that processors code-named Merom, Conroe and Woodcrest would not be based on the NetBurst architecture that powers current Intel Pentium 4 and Intel Xeon chips. Besides new architecture, which is expected to feature shorter pipeline and high performance per clock, the chips will also sport capabilities like virtualization capabilities, LaGrande technology, 64-bit capability in addition to EDB, EIST and iAMT2.
The code-named Merom processor will feature 14-stages pipeline, down from 31 or more stages found in current Intel Pentium (Prescott) designs, 4-issue out-of-order execution engine as well as improved performance of the floating-point unit (FPU). This greatly showcases the substantial difference from the current NetBurst chips that have very deep pipeline and cannot boast with really high-performance FPUs. Furthermore, 14-stages pipeline is deeper compared to AMD Athlon 64’s 12-stages pipeline, which, on the one hand, allows slightly higher clock-speeds compared to the AMD64 architecture, but, on the other hand, may mean a bit lower efficiency.
