CMOS virtually immortal, Intel claims

PAOLO GARGINI kicked off the Developer Forum this afternoon by discussing how Intel regards nanotechnology.
Gargini, who directs technology strategy for Intel, said that cost was not the limited for CMOS technology. In 1993, he said a fab cost $.9 billion dollars for a 200mm wafer size, in 1998 a fab cost $2 billion and in 2003 a fab costs $3 billion. That's because of the ability to shrink the process and increase the wafer size, he said.

But in reality the cost versus the revenues match each other. Moore's Law is a mix of business and technology. Ten years after he started talking about this law, he saw no reason to expect the rate of progress in the use of smaller dimensions in complex circuits to decrease in the near future.

After 40 years, Moore's Law is holding true, said Gargini. The two times model every two years remains a very good assumption.

Even in the most pessimistic forecast Moore's Law will continue to be true, he said. The average price of transistors has seen a seven orders of magnitude reduction in price per transistor since 1968.

Gargni showed a slide which showed that by 2007 Intel could move to 45 nanometre technology, and by 2009 to 32 nanometres, with gate lengths of 25 nanometres and 18 nanometres respectively.

In 2011, Intel may be able to move to 22 nanometre processes which like the 65nm and the 45nm tech will use high k dielectrics and have a metal gate electrode.

A 90 nanometre transistor is half the size of the influenza virus. But is this nanotechnology? He said that Intel had originally thought that between 2005 and 2014 there would be equivalent scaling. Traditional transistors have leakage of gate oxide, increasing parasitic resistance, and punch through in conductive substrates.

Intel is tackling these problems by introducing new materials with a higher dielectric. It's been demonstrated but no production so far. He said it's like wine, it gets better with age. We don't think wine gets tweaked, but we think that's what he means.

Intel's 90 nanometre technology included strain techniques. That means a fster electron flow without changing the voltage. Hole mobility gives improved transistor performance. By 2004, using this technique, Intel was able to improve performance without having to change the basic geometry.

It took 12 years to put strained silicon into manufacturing. The 65 nanometre technology will also use strained silicon.

Trigate transistors is still being experimented with, he said. But it's not just an idea structure, but has them built, although it isn't needed yet, and Intel might wait for five years before implementing it.

This kind of device will be a nano device, which may have silicon nanowires defined by lithography. These could be chemically synthesised with diameters of less than 20 nanometres.

Intel is still investigating the feasibility of using carbon nanotubes, which he described as rolled up graphene sheets with dimensions of perhaps one to 25 nanometres depending on how they're made. Intel is also experimenting with compound semiconductor transistors using Si GaAs substrate for epitaxial growth. CMOS will contine for between 15 to 20 years and he claimed that Moore's Law could be extended indefinitely via new architectures, heterogeneous integration, and three dimensions. We're talking about between 2013 to 2019 here.

Intel is preparing for other concepts like molecular self assembly, driven by two sided organic surfactant molecules. The 3D interconnects will help by improving RC delay and power consumption by reducing wire lengths. Carbon nanotube interconnects allow higher currents to flow, but right now are difficult to use to build integrated circuits. The firm has several research programmes to bring these materials from the laboratories to the factories.

And what happens after 2020, when CMOS may run out? Intel has ideas like spintronics. Spintronics is not, we are assured, an Intel internal name for public relations.