As some of you might remember, vendors were trying to get Sata 6G working for the launch of the LGA1156-P55 platform, but due to instability issues (chip was not mature enough) no one actually implemented this technology. With the new Marvell chip, the SE9128, these instability issues are solved and, in addition to this, it now has Raid0 support, something which was not present on the SE9123 chip.
During the presentation a lot of figures were shown which proved that Sata 6G was indeed much faster. Do note that all these figures were synthetic benchmarks and, for instance, no windows boot time or in-game scene loading. We’ll try to provide some early Sata 6G performance data once the hardware is available. I didn't note down the exact numbers as I made the incorrect assumption that the presentation would be handed out on USB sticks afterwards, but I did make some notes on the performance and future products.Overall performance going from SATA 3G to SATA 6G was roughly 10%
Both Seagate and Western Digital hard disk drives will be equipped with a Marvell chip.
SSD variants will be available in Q1 2010
This new technology will most likely be implemented in the Intel chipset in Q4 2011/Q1 2012. It's widely assumed (and possibly confirmed *wink*) that this chipset will be named P65.
Before we jump to the conclusive part of this small article, have a quick glance at the SE9128 architectural scheme a few lines above. The smart guys and girls under us will notice that the maximum theoretical input bandwidth exceeds the maximum possible output data by a very large margin. As the Marvell Sata controller has to be connected to the CPU in some way, most vendors will opt for a solution that uses one of the PCIe lanes of the P55 chip; a 5Gbps PCIe 2.0 x1 lane. The problem is, however, that this new technology is Sata 6Gbps. In other words, the input bandwidth is exceeding the output from the moment you hook up one drive. Let alone what happens with 2 or more drives attached to the controller.
So, what's the solution?
One of the great innovations of the LGA1156-p55 platform is that the IOH moved into the processor, on the non-core die. A part of the IOH is the PCIe connection of which there are two available on any Lynnfield processor: either x16 or x8 x8 configuration.
Now, Gigabyte uses one of those PCIe lanes to connect to the Marvell SE9128, this increasing the SE9128-to-processor bandwidth and reducing the latency. The first benefit is pretty obvious, the second maybe a bit less. In short, the normal design requires two buses to transfer the data: one from the Marvell to P55 (PCIe) and one from the P55 to the CPU (DMI). In Gigabyte's design, the only bus is the PCIe bus in between Marvell controller and processor, which has the same clock frequency (and thus latency) as the PCIe bus from Marvell to P55.
We inquired Gigabyte about the effect of the Marvell data on the graphics card performance in crossfire mode. Apparently, Gigabyte made it possible that if the bus is saturated with VGA data, the data is transferred via the P55 again. Interference should be non-existing. We also inquired about the temperature of the P55/X58; as data throughput increases, temperature should increase as well. The answer was an expected "you always need to cool the components", although possibly more obligatory than usual.