The following admendments pertain to my article which first, was an "opinion" an "hypothesis" and if their are those who wouldn't even consider it an educated guess, simply my theory.
1.) To correct two industry inaccuracies: Current costs to build and maintain a fab for .13 micron production can exceed $2.5-billion not $1.6-billion as I incorrectly wrote. Also I didn't mean to suggest we are currently surpassing the 157nm photolithographic manufacture process, this was temporally incorrect. And I won't claim to have first hand knowledge of this, as I was actually unsure if "soft lithography" (248nm) was still utilized or if the industry has begun 193nm process for .13micron fab's. I want to thank those who clarified that .13 micron gate width is currently achieved by a 248nm process. Finally in so far as EUVL, this process will not be implemented until .032micron, which I'm currently writing about in a related article. 30GHz by 2007, may be more wishful thinking on my part, none-the-less, 15GHz to 20GHz may be more accurate, which will be explained in this upcoming article.
2.) Pertaining to Austin's article at lowyat,net, not only did I extrapolate from this, but my promulgation of it, was my choice and whether that artcile contains inaccuracies, I take full responsibility for what I wrote. There have been a plethora of unprovoked attacks by certain individuals claiming to have first-hand knowledge of microprocessor manufacturing, and AMD's Sticker CPUID system. And I appreciate your clarification where I expounded incorrect information. However, there's no need for attacking those of us, who in the absence of esoteric, "inside" knowledge resort to inductive logic in our conclusions. Perhaps all my premises were incorrect, do not flame me in effigy as if I intentionally am perpetuating misinformation. Why is it certain "experts" feel the need to resort to insultive language in their criticims? If your so offended, by what I clearly indicate is "theory" then take the time you spend being insultive, and write an article on a monthly basis, educating us "laypeople". There's constructive criticism, and there your displacing some pent up hostility, which I won't graciously accept. I can understand your frustration in the misinformation so prevelant in hardware forums, however; reducing my efforts to dirt, won't necessarily resolve that issue. After all, without dirt there'd be no silicon, and nothing to argue over. I do understand after spending 8 hours in a highly caustic environment, the last thing on your mind is searching forums looking to educate people on a subject your attempting to forget until the next shift. And on that subject I want to thank Wingznut at Anandtech for being so gracious in his clarification on certain points. To all the condescending flamers; you could learn much about etiquette from Wingznut. Intellectualism encapsulates much more then raw facts, it's also an awareness of social graces, and avoiding ignoble obtrusiveness.
3.) Finally in my presumption there may have been a lens misalignment or some other anomally in the manufacturing process, in my statement; K - R outer areas of the wafer inutile....number of variables...which can have detrimental effects on the end-product...as plentiful as dust particles in the air... my quoting of the BYTE article implies I'm familiar with the fact; "each cubic foot contains no more than one 0.1-micron-size particle" although that particular quote wasn't included, it's in the next paragraph of the BYTE artcile.
In so far as my assumption of microprocessor manufacturing aiming towards several speeds I was obviously incorrect. And I also want to clarify, my claiming to have emperically verified processors, my statement was semantically ambiguous. The emperical method, I used to collect data, was from almost two months of querying Tbred owners, examining threads, and recording end-users results. The margin for error in this method, is (upon further examination) replete with potential inaccuracies. Albeit an earnest attempt to compile data, it lacks the rigorous standards a control group or some strict "hands on" test criteria would have provided.
In so far as manufacturer's photolithographic methods aiming for strict uniformity over the entire wafer, this is much more realistic then my promulgating the "center wafer purity" theory. I'm grateful my initial interpretation was in fact correct. I not attempting an ad hoc retraction. I made the assertion and it was incorrect. Only, in the absence of my early asssertions being validated by "insiders," I swayed in my convictions. That's one reason I attempt to write, from a scientific or theoretical stance. Had I not made the Inductive Leap, it would not have coerced facts to the surface. I'm not afraid to be wrong, which is why I took the risk to expound such a theory, however; I'm troubled at the "impatience" latent in the keystrokes of many of my critics. Therein lay a plethora of psychological implications.
Perhaps it's the frustration in having to conceal confidential manufacturing methods. And with the propagation of so many stupefying theories (mine included) their simply pulling their DSL connects out, having to remain silent. In fact, there's now a part of me, in utter panic believing all I've suceeded in doing, is revealing the best kept secret overclockers have known for years. After all we've put years of erudition, and invested a significant amount of money truly empirically verifying certain esoteric manufacturing secrets, which represent the Holy Grail to the avid Overclocker. And I just gave it all away.
Will my article do no more then force AMD to lock it's multipliers? Will I become infamous as the man who snatched the Holy Grail from Overclockers? If so, then in that case, I'll flame myself in effigy. Again I want to thank Wingznut. I want to thank everyone at Madshrimps, (especially jmke) and especially Extremesys, all those who offered kind words, and those who took the time to criticize constructively. Stay tuned for my next article (completed, and I'm editing) which takes an indepth look into the transition from "Soft Photolithography" to EUVL, and considerations for LADI (developed at Princeton). I "theorize" (oh boy) as to the obstacles confronting the industry's rapid devlopment:
"...with 90 nm DRAM half-pitch and 37 nm microprocessor gate lengths by the end of 2004, and perhaps even in 2003. This acceleration has come at a cost...as less time between device generations gives limited time to prove the reliability of new materials, processes and products. As one consequence, the industry is far less likely to make drastic changes in materials — in both front-end transistor materials and back-end dielectrics — than it might have with a larger R&D time frame."
Laura Peters, SemiConductor International.Add a comment to this editorial