Test setup

For our little DFI adventure we put together the following test system:

Test Setup
CPU	Intel E6700 Core 2 Duo Cooled by TTIC "Big"
Mainboard	DFI Lanparty UT 680i LT SLI-T2R
Memory	2x 1Gb Teamgroup Xtreem PC6400C3 2x 1Gb OCZ PC8500 Reaper HPC 2x 1Gb OCZ PC9200 FlexXLC 2x 1Gb Corsair Dominator PC8888C4 2x 1Gb G.Skill PC8500C5 2x 1Gb OCZ PC6400C3 Flex XLC 2x 1Gb Corsair Dominator PC6400C3F
Other	Silverstone TJ09 Temjin Tower Case BFG 8800GTX (SLi) LG DVD-rom drive Wester Digital Raptor WD740 SATA OCZ ProXstream 1kW Watt PSU

The 680i and its test methodology

As we explained at the start of our review, the board of choice in this case is DFI's 680i board. This board was recently reviewed here, and for more information about the board itself I'd like to point you in that direction. However, some starting remarks have to be made as this board provides us with specific behavior when overclocking memory and it has some specific quirks as well.

To start off with common knowledge, the 680i chipset provides the user with near independent memory overclocking possibilities, independent of the front side bus that is. With "near" I point to the fact that the overclocking actually is not independent at all, the chipset just provides us with a large amount of dividers and multipliers, thus providing almost any memory speed for a given front side bus. Again, almost is the right word, as negative dividers (where memory runs slower than the front side bus) are not present on the DFI board.

Secondly, keep in mind that not all dividers are made equally. Some dividers are faster than others, some dividers offer better overclocking headroom than others, and some dividers do not seem to work at all. The fastest of any divider is very simple: for the DFI board it is the straight, synced or 1:1 divider where the memory runs exactly as fast as the front side bus.

Finally, the 680i boards were the first Intel boards that made it possible to set the "command per clock" settings for memory at 1 cycle instead of the usual 2 cycles. Nowadays, P35 and X38 can do this as well, but without a real performance advantage. A command rate of 1 cycle does give a large performance advantage on 680i however. Of course, on the downside, memory does not OC to the same level with a CR of 1 vs 2.

On the quirky side, the DFI has what we call "front side bus holes", which means that, when you overclock the board, you can suddenly bump into a brick wall at a certain frequency, whereas 10Mhz more can suddenly start working again. The difficult part in this is the fact that the "holes" sometimes differ by memory divider, so a hole in the 1:1 divider might not occur on another divider.

Another serious quirk is the fact that the DFI board refuses to clock memory higher than 1200Mhz (DDR), at least with the bioses we tried. For certain memory modules we knew absolutely for sure that they were able to reach 1300Mhz given the right voltage (and the voltages on the DFI are certainly adequate), but our board just refused. But even bigger was our surprise when we were testing the Dominator PC8888 modules for this review : our testing revealed that the board did not have absolute brick wall for memory at 1200Mhz, but only a brick wall at a cas ratio of 5 cycles. When tweaked to 4 cycles, our memory was able to complete full stability tests at or even over 1200Mhz... now how about that !

A last annoying quirk is the fact that board performance scaling with increasing front side bus is limited: performance is extremely good up to 450 front side bus, but above 450Mhz the performance drops dramatically, in my case anyway. The board does scale with dual core processors to 500 front side bus and beyond, but performance is severely lacking. It's possible however that a bios upgrade could solve this in the future.

---

All of the above remarks led to our three test settings, here they are :

Stock settings : we entered the bios and asked for optimized defaults, and just booted to windows. When doing this, our DFI board put the memory at 800Mhz automatically, but at very slow timings. The timings set by the DFI board were 5-5-5-15.

. Synched (1:1) memory performance @ 400 Mhz, cas 3 / 1T : as synched operation provides the best performance, we could not leave this out. High end memory will be able to scale beyond 400mhz with a cas ratio of three, and a command rate of 1 cycle.

. Unlinked (variable) memory performance @ 400 Mhz, cas 4/2T : because we would like to know how high our memory really clocks, we chose the cas 4 setting with a command rate of 2T. We would have liked to go for cas 5/2T, but as our board had trouble going beyond 1200Mhz for the memory at this setting, we ended up with cas 4.

---

After these three tests, we did two more to determine the maximum memory performance, in other words, to see how high we could overclock our test candidates. For the maximum memory performance we chose the synched (1:1) setting once more, as this is the best performing memory wise, and a cas ratio of 3 and 4 cycles, at a command rate of 1T. At these settings, it is very unlikely that memory will scale beyond 450Mhz, where the board's performance would drop, so the board is taken out of the equation.

Benchmark suite

As soon as we ensure full stability on all of the cas settings as shown on the previous page, we are ready to run our benchmark suite. This suite consists out of the following applications:

SiSoftware's S.A.N.D.R.A. 2007

Lavalys Everest 2.20

Maxon Cinebench 9.5

Futuremark 3D Mark 2006

Futuremark PC Mark 2005

Superpi 1.5, Xtremesystems edition

Game 1 : 3D Realms Prey demo ; benchmark by Hardware OC