A Tale of Two Companies and their Memory ControllersDDR3
is now upon us as is evident in the motherboard above a member of the Asus P5K Series
. For many, DDR3 is an eagerly anticipated light at the end of the DDR2 tunnel, a tunnel in which AMD seems stranded. For almost a year now Intel has enjoyed total market domination based on its Core Architecture, ironically they’ve possessed the wherewithal to build this CPU for approximately seven years. Core Architecture is essentially the great grand love child of PIII and Banias in a dual core package. In the years following PIII, AMD rejoiced in a healthy performance advantage based on their Quantispeed architecture vs. Intel's Net Burst.
When A64 hit the market with its on-die memory controller this performance advantage was solidified. Meanwhile in Santa Clara a Coup ensued resulting in an over zealous Marketing Department with million dollar mortgages stormed the R&D facility, taking hostage Intel engineers. For the next five years engineers were forced to adopt an ad hoc
"extend a pipeline" increase speed manufacturing mantra. Intel took advantage of the layperson's ignorance of IPCs and sold them on raw speed. Jon Stokes of ars technica
described the scenario perfectly in his 2004 article The Pentium: An Architectural History of the World's Most Famous Desktop Processor (Part II)
As a result of inflated clock speeds coming out of Santa Clara, AMD was forced to implement a Performance Rating system. Perhaps no other journalist understood the relationship between these two designs as well as Van Smith of Vans Hardware Journal
. He summarized the two camps as "AMD's Braniac vs. Intel's Speed Demon" approach to chip design. As far back as his Althlon XP 2000
article he made some astute predictions. These culminated with his 2004 article on Prescott entitled; Pentium 4 is dead
hen came DDR2. By the time AMD finally adopted DDR2 on their AM2 platform it was too little, too late. AMD's decision to re-design their memory controller simply to accommodate the DDR2 standard so late in the game saw their own version of ad hoc
engineering. We can only speculate as to the reasons AMD would bastardize their on-die memory controller for DDR2 yet leave their core frequency to flop around at 200MHZ. In the interim Overclockers had discovered the Pentium-M which sealed AMD's fate. Once the dual core Yonah came along and AOpen gave us their i975Xa-YDG
PC-Enthusiasts had a taste of what was possible. Santa Clara was back in the business of building processors. This created a ground swell of anticipation for the rumored Core Duo desktop.
Today as we test two very popular 2GB kits of DDR2-1000Mz from Super Talent and Crucial we discover the point of departure from AM2's core frequency which is compatible with DDR-800MHz and an on-die memory controller's propensity for tighter latencies. At 1000MHz the memory featured may be just a bit fast for AM2 plug and play compatibility and too slow for Intel Core Architecture based on 266MHz FSB. As DDR2 now surpasses 1333MHz, Core Duo is approaching its first birthday and as a child prodigy influencing the entire industry. Core Architecture takes advantage of a chipset released prior to its introduction and while this may not be extraordinary in and of itself, in one fell swoop owners of 975X chipset motherboards who were struggling to attain a 300FSB one day found themselves surpassing 400FSB the next. Conroe takes full advantage of the 975X especially its memory controller outlined below.
This is where a traditional North Bridge Memory Controller Hub has its advantages, foremost being versatility. The fact Intel has used their Socket-T platform and the 975X chipset through so many iterations of processors has given them tremendous flexibility. From Prescott to Kentsfield Intel can offer many CPU / NB combinations supporting different technologies while AMD must re-design to adapt. For the first time in years Intel continues to lead AMD in TDP efficiency while increasing FSB speeds. For our Intel tests today we chose the Asus P5W DH Deluxe/WiFi based on the i975X chipset.
The 975X is a reiteration of the archetypal North Bridge > South Bridge chipset. The Memory Controller is housed in the North Bridge (NB) and is known as the Memory Controller Hub (MCH). In this design the CPU is isolated from main memory and only communicates directly with the MCH, which in turn communicates with main memory. The information path between the CPU and NB is known as the Front Side Bus (FSB) and there are benefits as well as detriments in this type of circuitry. Critics of this memory sub-system see the additional wait state at the MCH as a substantial hit on performance compared to a system which eschews the NB-MCH. Supporters of the traditional NB have only to cite Conroe's success on their 975, 965 and now the 935 chipsets each offering unique features.O
n the AMD side of things we have the NVIDIA nForce-590 chipset. Following in the footsteps of the nForce 4 ULTRA/SLI the 500 series is the new improved version. What's different between the nForce-4 and nForce-5 is the presence of a "North Bridge". Not your traditional NB per se
instead this is known as the SPP responsible for PCIe traffic. For AMD testing with Crucial Ballistix and Super Talent I've chosen the Asus M2N32-SLI Deluxe/WiFi based on the NVIDIA nForce-590 chipset seen below.
Given the contrast between our chipsets, comparing memory performance across platforms would be synonymous with comparing chipsets. For that reason I've kept tests separate until the final page where I compare performance using those benchmarks which I felt thoroughly isolated memory performance. Lest we forget this review is to re-visit two kits of memory which offer some of the lowest latencies up to 800MHz and beyond and provide an outstanding value.Onto the Usual Suspects ->