Changes have been also made regarding the cache hierarchy with dedicated 64KB L1 instruction and data caches, we do have 512KB dedicated L2 cache per core and 8MB of L3 cache shared across four cores. The cache is enhanced with a learning prefetcher that speculatively harvests application data into the caches so they are practically available for immediate execution. These changes are assuring up to 5X greater cache bandwidth into a core. This type of design enhances the Zen architecture's throughput.

When talking about efficiency, the new Ryzen processors are built on the more power-efficient 14nm FinFET process; in more detail, the Zen architecture is using the density-optimized version of the Global Foundries 14nm FinFET process and this fact permits for smaller die sizes and lower operating voltages. The new Zen microarchitecture does incorporate some of the latest low-power design technologies:

-micro-op cache for reducing power-intensive faraway fetches

-aggressive clock gating to zero out dynamic power consumption in minimally utilized regions of the core

-a stack engine for low-power address generation into the dispatcher.

Moving on to the scalability aspect, Zen architecture does start with the CCX (CPU Complex) which is a native 4C8T module; each CCX does come with 64K L1 I-cache, 64K L1 D-cache, 512KB of dedicated L2 cache per core and 8MB of L3 cache shared across all cores. Each core that is contained in the CCX may optionally come with SMD for additional threads.

Depending on the SKU, more than one CCX can be present in a Zen-based product; when strictly referring to the Ryzen 7 Series, these do come with two CCXes, which does mean a total of 8 cores and 16 threads. Individual cores within the CCX may be disabled by AMD and the CCXes communicate across the high-speed Infinity Fabric. Thanks to this modular design, AMD can scale core, thread and cache quantities as necessary in order to cover all the market segments.