Haswell is a brand new architecture, typical as this CPU is a Tock design. For those not acquainted with the Tick-Tock Intel principle. A Tick is a die size shrink, minor changes, while a Tock refers to something completely new. Hence why the Haswell name has got nothing to do with the previous Sandy and Ivy-Bridge CPUs.
With Haswell Intel continues on the 22nm manufacturing process. Upcoming processor releases, might receive the die shrink treatment. For the transistors also no changes, Intel still utilises the Tri-Gate 3-D transistors, derived from the Ivy-Bridge generation. The Die size has been slightly increased from 160mm² to 177mm², while the transistor count went down from 1.6Billion to 1.4Billion. For the most I7 versions the Level 3 cache remains at 8MB, alike the Ivies. Only the BGA 4770R receives a mere 6MB L3 cache. The hyperthreading-less i5 series get equipped with 6MB L3 cache, with exception of the 4MB L3 4570T CPU, is the standard. Biggest novelty is the integration of the motherboards VRM, inside the CPU's Die, this to minimise the power consumption. But a bit more on that topic on the next page.
Intel as usual tries to increase the performance per instruction versus the previous generation, but head objective is to manufacture a far more energy efficient platform. To achieve that goal the integration of the VRM plays the biggest part.
However there's more to Haswell that makes it quite different from the previous S1155 CPUs. Looking at the CPU-Z screens we already notice that the Haswell CPU's run at idle as low as 800MHz. Spot the Vcore, with SB we were still around the 1.0V mark, now it's dropping even as low as 0.7V. New is also the dynamic ring bus frequency, maxing out as high as the CPU frequency. In CPU-Z the Ring bus frequency is read out as NB Frequency. Some mainboard manufacturers even refer to it as Uncore ( from socket 1366 ) as it's shares similarities with the Nehalem concept.
With Sandy and Ivy Bridge, the L3 Cache ran at the same speeds as the cores. This allowed for very fast and low latency throughput. The integrated Graphics core was running on it's own proper frequency. With Haswell we got 3 clock domains again: the cores, the ring bus and the iGPU frequency all got their own operating speeds. This allows for finer control of the various on Die components, thus again resulting in a power reduction whenever possible.
Talking about the Cache, we see a nice improvement in the bandwidth for the L1 and L2 cache, however the size of the different caches remain unchanged. The L3 cache, due to it's independant operating speeds will be slightly less effective on the Haswell architecture.